1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly relates to a semiconductor memory device including an SRAM (Static Random access Memory) cell.
2. Description of Related Art
An SRAM is known as a memory able to operate at a high speed. In the SRAM, when a word line is activated, all memory cells, which include a target memory cell and are connected to the word line, are activated. For this reason, the charging and discharging are carried out not only to a bit line pair of the target memory cell but also to bit line pairs of non-target memory cells. The charging and discharging carried out to the bit line pairs of the non-target memory cells cause unnecessary power consumption.
As a technique for reducing power consumption in an SRAM, a semiconductor memory device is disclosed in JP-A-Heisei 8-167291 (Patent literature 1, corresponding to U.S. Pat. No. 5,757,689(A)). FIG. 1 directly shows FIG. 1 of JP-A-Heisei 8-167291 without changing reference numerals, symbols and the like (accordingly, the reference numerals, symbols and the like are valid only in FIG. 1 and do not relate to reference numerals, symbols and the like of an embodiment of the present invention described below). The semiconductor memory device includes a memory cell array where a plurality of memory cells (M00, M01, . . . , M10, M11, . . . ) are arranged in a matrix shape, thus activates addressed word lines (EWL0, OWL0, . . . ) to operatively connect the memory cells (M00, M01, . . . ) to bit lines (B0, /B0, B1, /B1, . . . ), and then lets data be sent and received. The semiconductor memory device includes at least two word lines (for example, EWL0 and OWL0) to the same row address, the word lines being controlled by a column address. The memory cells (for example, M00, M01, . . . ) belonging to the same row (for example, 0th row) have the same row address, and are connected to the different word line (for example, EWL0 or OWL0) of the above-mentioned at least two word lines (for example, EWL0 and OWL0) having different column addresses. That is, in the semiconductor memory, the number of bit line pairs to be charged and discharged is reduced by using a plurality of word lines, and thus the number of times of unnecessary charging and discharging is reduced. In this manner, the power consumption is reduced.
Meanwhile, after the technology node 90 nm, in an SRAM, a horizontal memory cell layout has been often employed. As a technique of a horizontal memory cell layout, a semiconductor memory device is disclosed in JP 3523762(B2) (Patent literature 2, corresponding to U.S. Pat. No. 5,930,163(A)). FIGS. 2A, 2B, and 2C directly show FIGS. 1, 2, and 16 of JP 3523762 (B2), respectively, without changing reference numerals, symbols and the like, (accordingly, the reference numerals, symbols and the like are valid only in FIGS. 2A, 2B, and 2C, and do not relate to reference numerals, symbols and the like of the embodiment of the present invention described below). The semiconductor memory device includes a first inverter, a second inverter, a third N-channel type MOS transistor (N3), and a fourth N-channel type MOS transistor (N4). The first inverter includes a first N-channel type MOS transistor (N1) and a first P-channel type MOS transistor (P1). The second inverter includes a second N-channel type MOS transistor (N2) and a second P-channel type MOS transistor (P2). An input terminal of the second inverter is connected to an output terminal of the first inverter, and an output terminal of the second inverter is connected to an input terminal of the first inverter. In the third N-channel type MOS transistor (N3), the source is connected to the output terminal of the first inverter, the drain is connected to a first bit line (BL), and the gate is connected to a word line (WL). In the fourth N-channel type MOS transistor (N4), the source is connected to the output terminal of the second inverter, the drain is connected to a second bit line (/BL), and the gate is connected to the word line (WL). Respective arrangement directions of source and drain of: the first, second, third, and fourth N-channel type MOS transistors (N1, N2, N3, and N4); and the first and second P-channel type MOS transistors (P1 and P2) are configured so as to be parallel to a boundary line between: a P-well region (P well) where the first, second, third, and fourth N-channel type MOS transistors (N1, N2, N3, and N4) are formed; and an N-well region (N well) where the first and second P-channel type MOS transistors are formed. A first polycrystalline silicon wiring layer (PL2) used for the gate of the third N-channel type MOS transistor (N3) and a second polycrystalline silicon wiring layer (PL1) used for the gate of the first N-channel type MOS transistor (N1) and for the gate of the first P-channel type MOS transistor (P1) are arranged in parallel to each other. A third polycrystalline silicon wiring layer (PL4) used for the gate of the fourth N-channel type MOS transistor (N4) and a fourth polycrystalline silicon wiring layer (PL3) used for the gate of the second N-channel type MOS transistor (PL3) and for the gate of the second P-channel type MOS transistor (P2) are arranged in parallel to each other.
The inventor has now discovered the following facts. As described above, in the horizontal memory cell layout (FIGS. 2A and 2B), the SRAM cell has a structure that sandwiches the N-well with the P-wells. Then, the load transistors (P1 and P2) are arranged in the center of the SRAM cell, and the access transistors (N3 and N4) and driver transistors (N1 and N2) are arranged on both sides of the SRAM cell. In the horizontal memory cell layout, the word line (WL) serving as the input of the access transistors (N3 and N4) is shared with an adjacent cell. That is, in the horizontal memory cell layout, the word line (WL) passes in the third wiring layer, and is connected to the polysilicons (PL2 and PL4) via contacts on the boundary positions of the cell (end portions in horizontal directions of FIGS. 2A and 2B). These contacts and polysilicons of the word line (WL) are shared with the adjacent SRAM cell.
In the case of an SRAM cell whose contact of a word line and the like are shared with an adjacent cell as exemplified as the above-mentioned horizontal memory cell layout, the word line cannot be switched to another word line in each single cell independently. That is, the word lines cannot be switched in an arbitrary position in the cell array. Accordingly, it is impossible to employ the technique for reducing the number of bit line pairs to be charged and discharged by using a plurality of word lines as shown in the configuration (FIG. 1) disclosed in JP-A-Heisei 8-167291. As the result, in the SRAM cell whose contact of the word line and the like are shared with the adjacent cell, it becomes difficult to intend to reduce the power consumption by reducing the number of times of unnecessary charging and discharging. As a countermeasure, a method to change the shape of SRAM cell and a method to dividing the memory cell array can be considered. However, there are problems that the former requires an effort of processes for memory cell development and that the latter causes deterioration of an area efficiency.